A phase-locked loop (PLL) typically includes a loop filter, and the loop filter typically includes an integration capacitor. Where the PLL is manufactured using complementary metal-oxide semiconductor (CMOS) processes, the gate capacitance of an n-channel field-effect transistor (FET) can be used as the integration capacitor. As advances are made in CMOS processing technology, however, gate oxide dielectric thickness is becoming thinner. Significant current leakage can occur from the gate electrode, through the thin gate oxide, and to the inversion channel of the transistor.
FIG. 1 (prior art) illustrates an example of a PLL 10 of the prior art that includes a phase detector 11, a charge pump 12, a loop filter 13, a voltage-controlled oscillator (VCO) 14 and a frequency divider 15. Phase detector 11 compares the phase of a reference signal REFCLK 16 to the phase of a feedback signal FBCLK 17 and generates phase-error signals. Feedback signal 17 is a “divide-by-n” signal output by frequency divider 15. Frequency divider 15 divides the frequency of a clock signal 18 output by VCO 14. When the phase of feedback signal 17 lags behind that of reference signal 16, phase detector 11 generates an up control signal 19. When the phase of feedback signal 17 leads that of reference signal 16, phase detector 11 generates a down control signal 20. Charge pump 12 adds charge to its output lead 21 upon receiving up control signal 19 and drains charge from its output lead 21 upon receiving down control signal 20.
Loop filter 13 is typically a low-pass filter. Loop filter 13 filters out reference frequency sidebands introduced by phase detector 11 from the output of charge pump 12. Loop filter 13 has an integration capacitor 22 and a much smaller integration capacitor 23 that integrate the charge that is output by charge pump 12. VCO 14 receives the filtered output of charge pump 12. Upon receiving a higher input voltage, VCO 14 outputs clock signal 18 with a higher frequency. Clock signal 18 has a lower frequency when VCO 14 receives a lower input voltage. Thus, the frequency of clock signal 18 is proportional to the charge that accumulates on output lead 21 of charge pump 12. PLL 10 adjusts the frequency of clock signal 18 in response to measuring the phase difference between reference signal 16 and feedback signal 17 and thereby brings feedback signal 17 into phase lock with reference signal 16.
Current leakage across integration capacitors 22 and 23 introduces noise into the voltage signal supplied to VCO 14. Current leakage across integration capacitors can be reduced by using capacitors with metal plates. Realizing a capacitor of a given capacitance using a metal plate structure can require many times more semiconductor die area than realizing the capacitor using the gate capacitance of a FET. Moreover, the capacitance of metal plate capacitor structures can vary considerably from die to die and can be difficult to control.
Current leakage across integration capacitors can also be reduced by using transistors with thick gate oxides. A transistor with a thick gate oxide, however, provides less capacitance per unit of semiconductor die area as compared to a transistor with a thin gate oxide. Moreover, a thick gate oxide transistor typically has a higher threshold (“turn-on”) voltage, which limits the voltage range on the node of output lead 21. The limited voltage range on node 21 limits the range of frequencies over which the PLL can be locked.
FIG. 2A (prior art) shows a prior art PLL 25 that has been adapted to be stable over a wide frequency range. Like reference numerals in FIGS. 2A and 1 designate like or similar parts. Integration capacitors 26 and 27 of loop filter 13 are both realized using n-channel transistors. Capacitor 26 is coupled between a first node 31 and ground. First node 31 is the non-inverting input lead of a first voltage follower 28. Capacitor 27 is coupled between a second node 32 and ground. Second node 32 is the output lead of first voltage follower 28 and the non-inverting input lead of a second voltage follower 29. PLL 25 includes a second charge pump 30 that outputs a larger amount of charge onto second node 32 than charge pump 12 outputs onto first node 31. Charge that coarsely adjusts frequency thereby reaches VCO 14 faster than charge for fine adjustment of frequency. This reduces the tendency of clock signal 18 to overshoot the desired phase correction and makes the loop more stable. PLL 25 nevertheless suffers from noise caused by current leakage through integration capacitors 26 and 27.
FIG. 2B (prior art) is a waveform diagram that illustrates noise in the control voltage on a third node 33 of PLL 25 that is coupled to the input of VCO 14. FIG. 2B also illustrates voltage amplitudes for various other signals on PLL 25 when feedback signal 17 lags reference signal 16 by a time period 34. Current leakage through integration capacitors 26 and 27 causes a jitter in the control voltage on third node 33. Without the effects of current leakage, the control voltage on third node 33 would have a relatively stable average amplitude 35.
A method is thus desired that reduces the effects of current leakage through integration capacitors, but that does not negate the advantages of using FET transistors to form those integration capacitors in phase-locked loops.